As is conventionally known, a plurality of (for example, two) types of error correction are applied to storage devices in order to improve the reliability of the devices. Furthermore, in recent years, a memory system with multiple channels has been known which includes a memory typified by a NAND flash memory and which carries out a plurality of access commands in parallel. In general, for each logical page in a logical block, such a memory system can be accessed via a plurality of channels in parallel.
Thus, it is expected that a plurality of types of error correction are applied to a memory system with multiple channels. For example, it is expected that if an uncorrectable error occurs even by use of an error correction code (ECC), the error location is corrected based on inter-channel data. To enable such correction (hereinafter referred to as inter-channel error correction), any one of a plurality of channels may be allocated for storing error correction data for the inter-channel error correction (this channel is hereinafter referred to as an error correction channel). In this case, application of the error correction channel needs to avoid affecting the parallelism of data reads.